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ds05-20872-1e fujitsu semiconductor data sheet page mode flash memory cmos 16m (2m 8/1m 16) bit mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n features ? single 3.0 v read, program and erase minimizes system level power requirements ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with mask rom pinouts 48-pin tsop (i) (package suffix: pftn-normal bend type, pftr-reversed bend type) 44-pin sop (package suffix: pf) ? minimum 100,000 program/erase cycles ? high performance 25 ns maximum page access time (75ns maximum random access time) ? an 8 words page read mode function ? sector erase architecture one 8k word, two 4k words, one 112k word, and seven 128k words sectors in word mode one 16k byte, two 8k bytes, one 224k byte, and seven 256k bytes sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically programs and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode ?low v cc write inhibit 2.5 v (continued) embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
2 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 (continued) ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector protection hardware method disables any combination of sectors from program or erase operations ? temporary sector unprotection temporary sector unprotection with the software command ? 5v tolerant (data, address, and control signals) ? in accordance with cfi (c ommon f lash memory i nterface) n pac k ag e marking side marking side 48-pin plastic tsop (i) (fpt-48p-m20) (fpt-48p-m19) 44-pin plastic sop (fpt-44p-m16)
3 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n general description the mbm29pl160td/bd is a 16m-bit, 3.0 v-only flash memory organized as 2m bytes of 8 bits each or 1m words of 16 bits each. the mbm29pl160td/bd is offered in a 48-pin tsop (i), and 44-pin sop packages. the device is designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29pl160td/bd offers access times of 75 ns and 90 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29pl160td/bd is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29pl160td/bd is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each sector can be programmed and verified in about 2.0 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margins. any individual sector is typically erased and verified in 4.8 second. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29pl160td/bd is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 or by the toggle bit feature on dq 6 output pin. once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29pl160td/bd memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
4 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n flexible sector-erase architecture ? one 8k word, two 4k words, one 112k word, and seven 128k words sectors in word mode. ? one 16k byte, two 8k bytes, one 224k byte, and seven 256k bytes sectors in byte mode. ? individual-sector, multiple-sector, or bulk-erase capability. ? individual or multiple-sector protection is user definable. mbm29pl160td top boot sector architecture mbm29pl160bd bottom boot sector architecture sector sector size ( 8) address range ( 16) address range sa0 256 kbytes or 128 kwords 000000h to 03ffffh 00000h to 1ffffh sa1 256 kbytes or 128 kwords 040000h to 07ffffh 20000h to 3ffffh sa2 256 kbytes or 128 kwords 080000h to 0bffffh 40000h to 5ffffh sa3 256 kbytes or 128 kwords 0c0000h to 0fffffh 60000h to 7ffffh sa4 256 kbytes or 128 kwords 100000h to 13ffffh 80000h to 9ffffh sa5 256 kbytes or 128 kwords 140000h to 16ffffh a0000h to bffffh sa6 256 kbytes or 128 kwords 180000h to 1bffffh c0000h to dffffh sa7 224 kbytes or 112 kwords 1c0000h to 1f7fffh e0000h to fbfffh sa8 8 kbytes or 4 kwords 1f8000h to 1f9fffh fc000h to fcfffh sa9 8 kbytes or 4 kwords 1fa000h to 1fbfffh fd000h to fdfffh sa10 16 kbytes or 8 kwords 1fc000h to 1fffffh fe000h to fffffh sector sector size ( 8) address range ( 16) address range sa0 16 kbytes or 8 kwords 000000h to 003fffh 00000h to 01fffh sa1 8 kbytes or 4 kwords 004000h to 005fffh 02000h to 02fffh sa2 8 kbytes or 4 kwords 006000h to 007fffh 03000h to 03fffh sa3 224 kbytes or 112 kwords 008000h to 03ffffh 04000h to 1ffffh sa4 256 kbytes or 128 kwords 040000h to 07ffffh 20000h to 3ffffh sa5 256 kbytes or 128 kwords 080000h to 0bffffh 40000h to 5ffffh sa6 256 kbytes or 128 kwords 0c0000h to 0fffffh 60000h to 7ffffh sa7 256 kbytes or 128 kwords 100000h to 13ffffh 80000h to 9ffffh sa8 256 kbytes or 128 kwords 140000h to 17ffffh a0000h to bffffh sa9 256 kbytes or 128 kwords 180000h to 1bffffh c0000h to dffffh sa10 256 kbytes or 128 kwords 1c0000h to 1fffffh e0000h to fffffh
5 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n product line up n block diagram part no. mbm29pl160td/160bd ordering part no. v cc = 3.0 v -75 -90 max. address access time (ns) 75 90 max. page address access time (ns) 25 35 max. ce access time (ns) 75 90 max. oe access time (ns) 25 35 +0.6 v C0.3 v v ss v cc we ce a 0 to a 19 oe erase voltage generator dq 0 to dq 15 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb a -1 byte timer for program/erase
6 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n connection diagrams standard pinout tsop(i) (marking side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 byte a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 we n.c. a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce n.c. v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss n.c. fpt-48p-m19 reverse pinout (marking side) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ce a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 n.c. we a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 byte n.c. v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v ss v cc v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss n.c. fpt-48p-m20 v cc v ss we a 17 a 18 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce v ss oe dq 0 dq 1 dq 8 dq 9 dq 6 dq 13 dq 7 dq 14 dq 15 /a -1 v ss byte a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 n.c. 144 243 342 441 540 639 738 837 936 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 sop (marking side) fpt-44p-m16 dq 2 dq 5 dq 10 dq 12 dq 3 dq 4 dq 11 v cc
7 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n logic symbol 20 a 0 to a 19 we oe ce a -1 dq 0 to dq 15 16 or 8 byte table 1 mbm29pl160td/bd pin configuration pin function address inputs data inputs/outputs chip enable output enable write enable a -1 , a 0 to a 19 dq 0 to dq 15 ce oe we pin not connected internally device ground device power supply n.c. selects 8-bit or 16-bit mode byte v ss v cc
8 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n device bus operations table 2 mbm29pl160td/bd user bus operation (byte = v ih ) table 3 mbm29pl160td/bd user bus operation (byte = v il ) legend: l = v il , h = v ih , x = v il or v ih . = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. see table 7. 2. refer to the section on sector protection. 3. we can be v il if oe is v il , oe at v ih initiates the write operations. 4. v cc = 3.3 v 10% operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 auto-select manufacture code (1) l l h l l l v id code auto-select device code (1) l l h h l l v id code read (3) l l h a 0 a 1 a 6 a 9 d out standby h x x x x x x high-z output disable lhhxxxxhigh-z write (program/erase) l h l a 0 a 1 a 6 a 9 d in enable sector protection (2), (4) l v id lhlv id x verify sector protection (2), (4) l l h l h l v id code operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 auto-select manufacture code (1) l l h l l l l v id code auto-select device code (1) l l h l h l l v id code read (3) l l h a -1 a 0 a 1 a 6 a 9 d out standby h x x x x x x x high-z output disable l h h x x x x x high-z write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in enable sector protection (2), (4) l v id llhlv id x verify sector protection (2), (4) l l h l l h l v id code
9 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n functional description random read mode the mbm29pl160td/bd has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc - t oe time.) see figure 5.1 for timing specifications. when reading out a data without changing addresses after powe-up, it is necessary to input hardware reset or to change ce pin from "h" to "l". page read mode the mbm29pl160td/bd is capable of fast page read mode and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the mbm29pl160td/bd device is 8 words, or 16 bytes, within the appropriate page being selected by the higheraddress bits a 0 to a 2 (in the word mode) and a -1 to a 2 (in the byte mode) determining the specific word/ bytewithin that page. this is an asynchronous operation with the microprocessor supplying the specific word or byte location. the rondom or initial page access is equal to t acc and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to t pa c c . here again, ce selects the device and oe is the output control and should be used to gate data to the output pins if the device is selected. fast page mode accesses are obtained by keeping a 3 to a 19 constant and changing a 0 to a 2 to select the specific word, or changing a -1 to a 2 to select the specific byte, within that page. see figure 5.2 for timing specifications. standby mode the mbm29pl160td/bd has a standby mode, a cmos standby mode (ce input hel at v cc 0.3 v.), when the current consumed is less than 50 m a. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from standby modes. in the standby mode, the outputs are in the high-impedance state, independent of the oe input. if the device is deselected during erasure or programming, the device will draw active current until the operation is completed. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29pl160td/bd data. this mode can be used effectively with an application requesting low power consumption such as handy terminals. to activate this mode, mbm29pl160td/bd automatically switches itself to low power mode when addresses remain stable for 150 ns. it is not necessary to control ce , we , and oe in this mode. during such mode, the current consumed is typically 50 m a (cmos level). standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. output disable if the oe input is at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high-impedance state.
10 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. the intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the autoselect command may also be used to check the status of write-protected sectors. (see tables 4.1 and 4.2.) this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 (a -1 ). (see table 2 or table 3.) (recomend to set vil for the other addresses pins.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29pl160td/bd is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 7, command definitions. word 0 (a 0 = v il ) represents the manufactures code and word 1 (a 0 = v ih ) represents the device identifier code. for the mbm29pl160td/bd these two bytes are given in the table 4.2. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see tables 2 or 3.) if byte = v il (for byte mode), the device code is 27h (for top boot block) or 45h (for bottom boot block). if byte = v ih (for word mode), the device code is 2227h (for top boot block) or 2245h (for bottom boot block). in order to determine which sectors are write protected, a 1 must be at v ih while running through the sector addresses; if the selected sector is protected, a logical 1 will be output on dq 0 (dq 0 =1).
11 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 *1: a -1 is for byte mode. *2: outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. *3: outputs 01h at temporary sector unprotect and outputs 00h at non temporary sector unprotect. (b): byte mode (w): word mode table 4.1 mbm29pl160td/bd sector protection verify autoselect code type a 12 to a 19 a 6 a 1 a 0 a -1 * 1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29pl160td byte xv il v il v ih v il 27h word x 2227h mbm29pl160bd byte xv il v il v ih v il 45h word x 2245h sector protection sector addresses v il v ih v il v il 01h* 2 temporary sector unprotection x v il v ih v ih v il 01h* 3 table 4.2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufactures code 04h a -1 /00000000 00000100 device code mbm29pl160td (b) 27h a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z10100111 (w) 2227h 00100010 10100111 mbm29pl160bd (b) 45h a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z01000101 (w) 2245h 00100010 01000101 sector protection 01h a -1 /00000000 00000001 temporary sector unprotection 01h a -1 /00000000 00000001
12 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 table 5 sector address tables (mbm29pl160td) table 6 sector address tables (mbm29pl160bd) sector address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ( 8) address range ( 16) address range sa0 0 0 0xxxxx00 0000h to 03ffffh 00000h to 1ffffh sa1 0 0 1xxxxx04 0000h to 07ffffh 20000h to 3ffffh sa2 0 1 0xxxxx 080000h to 0bffffh 40000h to 5ffffh sa3 0 1 1xxxxx0c0000h to 0fffffh 60000h to 7ffffh sa4 1 0 0xxxxx10 0000h to 13ffffh 80000h to 9ffffh sa5 1 0 1xxxxx14 0000h to 17ffffh a0000h to bffffh sa6 1 1 0xxxxx 180000h to 1bffffh c0000h to dffffh sa7 1 1 1 00000 - 11011 1c0000h to 1f7fffh e0000h to fbfffh sa8 111111001f8000h to 1f9fffhfc000h to fcfffh sa9 111111011fa000h to 1fbfffhfd000h to fdfffh sa10 1111111x1fc 000h to 1fffffh fe000h to fffffh sector address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ( 8) address range ( 16) address range sa0 0000000x0 00000h to 003fffh 00000h to 01fffh sa1 000000100 04000h to 005fffh 02000h to 02fffh sa2 000000110 06000h to 007fffh 03000h to 03fffh sa3 0 0 0 00100 - 11111 008000h to 03ffffh 04000h to 1ffffh sa4 0 0 1xxxxx04 0000h to 07ffffh 20000h to 3ffffh sa5 0 1 0xxxxx 080000h to 0bffffh 40000h to 5ffffh sa6 0 1 1xxxxx0c0000h to 0fffffh 60000h to 7ffffh sa7 1 0 0xxxxx10 0000h to 13ffffh 80000h to 9ffffh sa8 1 0 1xxxxx14 0000h to 17ffffh a0000h to bffffh sa9 1 1 0xxxxx 180000h to 1bffffh c0000h to dffffh sa10 1 1 1xxxxx1c0000h to 1fffffhe0000h to fffffh
13 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 write device erasure and programming are accomplished via the command register. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of ce or we , whichever occurs later, while data is latched on the rising edge of ce or we pulse, whichever occurs first. standard microprocessor write timings are used. see figures 6 to 8. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29pl160td/bd features hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 10). the sector protection feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il , a 0 = a 6 = v il , a 1 = v ih . the sector addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. tables 5 and 6 define the sector address for each of the eleven (11) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 14 and 20 for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. otherwise the device will read 00h for an unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to v il in byte mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) represents the sector address will produce a logical 1 at dq 0 for a protected sector. see tables 4.1 and 4.2 for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29pl160td/bd devices in order to change data. the temporary sector unprotection mode is activated by command register. during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the mode is taken away using command register, all the previously protected sectors will be protected again. (see figures 20.)
14 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 notes: 1. address bits a 11 to a 19 = x = h or l for all address commands except or program address (pa) and sector address (sa). 2. bus operations are defined in tables 2 and 3. 3. ra =address of the memory location to be read. pa =address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa =address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. 4. rd =data read from location ra during read operation. pd =data to be programmed at location pa. data is latched on the rising edge of we . 5. the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 0 to a 10 byte mode: aaah or 555h to addresses a -1 to a 10 6. both read/reset commands are functionally equivalent, resetting the device to the read mode. table 7 mbm29pl160td/bd standard command definitions command sequence (notes 1, 2, 3, 5) bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset (note 6) word /byte 1xxxhf0h read/reset (note 6) word 3 555h aah 2aah 55h 555h f0h ra rd byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h 555h 90h byte aaah 555h aaah byte/word program (notes 3, 4) word 4 555h aah 2aah 55h 555h a0h pa pd byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase (note 3) word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend word /byte 1xxxhb0h sector erase resume word /byte 1xxxh30h temporary unprotect enable word 4 555h aah 2aah 55h 555h e0h xxxh 01h byte aaah 555h aaah temporary unprotect disable word 4 555h aah 2aah 55h 555h e0h xxxh 00h byte aaah 555h aaah
15 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 spa : sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd : sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1 . this command is valid while fast mode. *2 . addresses from system set to a 0 to a 6 . the other addresses are dont care. *3 . the data" 00h" is also acceptable. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. table 7 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read mode, the read/reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory contents occurs during the power transition. refer to the ac read characteristics and waveforms for specific timing parameters. (see figure 5.1 and 5.2.) autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufactures and device codes must be accessible while the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the last command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h for 16 (xx02h for 8) retrieves the device code (mbm29pl160td = 27h and table 8 mbm29pl160td/bd extended command definitions command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read cycle addr data addr data addr data addr data set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program *1 word 2 xxxh a0h pa pd byte xxxh reset from fast mode *1 word 2 xxxh 90h xxxh f0h *3 byte xxxh xxxh query command *2 word 2 55h 98h byte aah
16 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 mbm29pl160bd = 45h for 8 mode; mbm29pl160td = 2227h and mbm29pl160bd = 2245h for 16 mode). (see tables 4.1 and 4.2.) all manufactures and device codes will exhibit odd parity with dq 7 defined as the parity bit. the sector state (protection or unprotection) will be indicated by address xx02h for 16 (xx04h for 8). scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be perform margin mode verification on the protected sector. (see tables 2 and 3.) to terminate the operation, it is necessary to write the read/reset command sequence into the register and, also to write the autoselect command during the operation, by executing it after writing the read/reset command sequence. word/byte programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of the last ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (see figures 6 and 7.) the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (see table 9, hardware sequence flags.) therefore, the device requires that a valid address be supplied by the system at this time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 16 illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six-bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (preprogram function.) the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read mode. (see figure 8.) figure 17 illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six-bus cycle operation. there are two unlock write cycles, followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after a time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin.
17 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 multiple sectors may be erased concurrently by writing six-bus cycle operations on table 7. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 m s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 m s time-out window the timer is reset. monitor dq 3 to determine if the sector erase timer window is still open. (see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. resetting the device once excution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 10). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. (see figure 8.) the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector program time (preprogramming) + sector erase time] number of sector erase. figure 17 illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or program to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are dont cares when writing the erase suspend or erase resume commands. when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by data polling of dq 7 and the toggle bit (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address.
18 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode mbm29pl160td/bd has fast mode function. this mode dispenses with the initial two unlock cycles required in the standard program command sequence writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to the figure 22 extended algorithm.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to the figure 22 extended algorithm.) (3) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward- compatible software support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. following the command write, a read cycle from specific address retrives device information. please note that output data of upper byte (dq 8 to dq 15 ) is 0 in word mode (16 bit) read. refer to the cfi code table. to terminate operation, it is necessary to write the read/reset command sequence into the register.
19 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 write operation status notes: 1. performing successive read operations from any address will cause dq 6 to toggle. 2. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. 3. dq 0 and dq 1 are reserve pins for future use. 4. dq 4 is fujitsu internal use only. dq 7 data polling the mbm29pl160td/bd device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 18. for chip erase and sector erase, data polling is valid after the rising edge of the sixth we pulse in the six-write pulse sequence. data polling must be performed at a sector address within any of the sectors being erased and not at a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29pl160td/bd data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded program algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. see figure 9 for the data polling timing specifications and diagrams. table 9 hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded/erase algorithm 0 toggle 0 1 toggle erase suspend mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle (note 1) 00 1 (note 2) exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded/erase algorithm 0 toggle 1 1 n/a erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
20 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 dq 6 toggle bit i the mbm29pl160td/bd also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the device will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data can be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six- write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 1 m s and then stop toggling without the data having changed. in erase, the device will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit i for about 100 m s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle. see figure 10 and figure 19 for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions. the oe and we pins will control the output disable functions as described in tables 2 and 3. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit i are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the command may not have been accepted. see table 9: hardware sequence flags.
21 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at dq 2 . dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also table 10 and figure 15. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. notes: 1. performing successive read operations from any address will cause dq 6 to toggle. 2. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. word/byte configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29pl160td/bd device. when this pin is driven high, the device operates in the word (16-bit) mode. the data is read and programmed at dq 0 to dq 15 . when this pin is driven low, the device operates in byte (8-bit) mode. under this mode, dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. refer to figures 11 to 13 for the timing diagrams. data protection the mbm29pl160td/bd is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine to the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence. the device also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. table 10 toggle bit status mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase suspend read (erase suspended sector) (note 1) 11toggle erase-suspend program dq 7 toggle (note 1) 1 (note 2)
22 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if the embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not change the command registers. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write, ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power-up.
23 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 description a 0 to a 6 dq 0 to dq 15 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 2h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min. (write/erase) d7-4: volt, d3-0: 100 mvolt 1bh 0027h v cc max. (write/erase) d7-4: volt, d3-0: 100 mvolt 1ch 0036h v pp min. voltage 1dh 0000h v pp max. voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min. size buffer write 2 n m s 20h 0000h typical timeout per individual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max. timeout for byte/word write 2 n times typical 23h 0005h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0015h flash device interface description 28h 29h 0002h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0004h erase block region 1 information 2dh 2eh 2fh 30h 0000h 0000h 0040h 0000h table 11 common flash memory interface code description a 0 to a 6 dq 0 to dq 15 erase block region 2 information 31h 32h 33h 34h 0001h 0000h 0020h 0000h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0080h 0003h erase block region 4 information 39h 3ah 3bh 3ch 0006h 0000h 0000h 0004h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0030h address sensitive unlock 0 = required 1 = not required 45h 0000h erase suspend 0 = not supported 1 = to read only 2 = to read & write 46h 0002h sector protect 0 = not supported x = number of sectors in per group 47h 0001h sector temporary unprotect 00 = not supported 01 = supported 48h 0001h sector protection algorithm 49h 0004h number of sector for bank2 4ah 00h burst mode type 00 = not supported 4bh 00h page mode type 00 = not supported 01 = 4 word page 02 = 8 word page 4ch 02h
24 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n absolute maximum ratings storage temperature .................................................................................................. C55c to + 125c ambient temperature with power applied .................................................................. C40c to +85c voltage with respect to ground all pins except a 9 , oe , and reset (note 1) ............ C0.5 v to +5.5 v v cc (note 1) ................................................................................................................ C0.5 v to +4.0 v a 9 , oe , and reset (note 2) ...................................................................................... C0.5 v to +13.0 v notes: 1. minimum dc voltage on input or l/o pins are C0.5 v. during voltage transitions, inputs may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and l/o pins are 6.0v. during voltage transitions,outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe , and reset pins are C0.5 v. during voltage transitions, a 9 , oe , and reset pins may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe , and reset pins are +13.0 v which may positive overshoot to 13.5 v for periods of up to 20 ns. voltage difference between input voltage and supply voltage (v in C v cc ) do not exceed 9 v. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges ambient temperature (t a ) mbm29pl160td/bd-75 ...........................................................................C20c to +70c mbm29pl160td/bd-90 ...........................................................................C40c to +85c v cc supply voltages mbm29pl160td/bd-75/90 ......................................................................+2.7 v to +3.6 v operating ranges define those limits between which the functionality of the device is quaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand.
25 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n maximum overshoot figure 1 maximum negative overshoot waveform +0.6 v C0.5 v 20 ns C2.0 v 20 ns 20 ns figure 2 maximum positive overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns 6.0 v 20 ns 20 ns figure 3 maximum positive overshoot waveform 2 v cc +0.5 v +13.0 v 20 ns +13.5 v 20 ns 20 ns note : this waveform is applied for a 9 , oe , and reset .
26 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n dc characteristics notes: 1. the l cc current listed includes both the dc operating current and the frequency dependent component. 2. l cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. applicable for only sector protection. 5. the input voltage must be input after vcc is valid. parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. C1.0 +1.0 a i lo output leakage current v out = v ss to v cc , v cc = v cc max. C1.0 +1.0 a i lit a 9 , oe , reset inputs leakage current v cc = v cc max., a 9 , oe = 12.5 v 35a i cc1 v cc active current (note 1) ce = v il , oe = v ih f = 10 mhz 70ma ce = v il , oe = v ih f = 5 mhz 40ma i cc2 v cc active current (note 2) ce = v il , oe = v ih 35ma i cc3 v cc current (standby) v cc = v cc max., ce = v cc 0.3 v, 5 a i cc4 v cc current (automatic sleep mode) (note 3) v cc = v cc max., ce = v ss 0.3 v, v in = v cc 0.3 v or v ss 0.3 v 5a i cc5 v cc active current (page read mode) ce = v il , oe = v ih 30mhz 12 ma 40mhz 15 ma v il input low level C0.5 0.8 v v ih input high level (note 5) 2.0 5.5 v v id voltage for autoselect,sector protection (a 9 , oe ) (note 4, 5) 11.5 12.5 v v ol output low voltage level i ol = 4.0 ma, v cc = v cc min. 0.45 v v oh1 output high voltage level i oh = C2.0 ma, v cc = v cc min. 2.4 v v oh2 i oh = C100 a v cc C 0.4 v v lko low v cc lock-out voltage 2.3 2.5 v
27 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 30 pf (mbm29pl160td/bd-75) 1 ttl gate and 100 pf (mbm29pl160td/bd-90) input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbols description test setup -75 (note) -90 (note) unit jedec standard t avav t rc read cycle time min. 75 90 ns t avqv t acc address to output delay ce = v il oe = v il max. 75 90 ns t prc page read cycle time min. 25 35 ns t pacc page address to output delay ce = v il oe = v il max. 25 35 ns t elqv t ce chip enable to output delay oe = v il max. 75 90 ns t glqv t oe output enable to output delay max. 25 35 ns t ehqz t df chip enable to output high-z max. 20 30 ns t ghqz t df output enable to output high-z max. 20 30 ns t axqx t oh output hold time from address, ce or oe , whichever occurs first min. 4 5 ns t elfl t elfh ce or byte switching low or high max. 4 5 ns figure 4 test conditions c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w notes: c l = 30 pf including jig capacitance (mbm29pl160td/bd-75) c l = 100 pf including jig capacitance (mbm29pl160td/bd-90)
28 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 ? write (erase/program) operations notes: 1. this does not include the preprogramming time. 2. this timing is for sector protection operation. parameter symbols description mbm29pl160td/bd unit jedec standard -75 -90 t avav t wc write cycle time min. 75 90 ns t avwl t as address setup time min. 0 0 ns t wlax t ah address hold time min. 45 45 ns t dvwh t ds data setup time min. 35 45 ns t whdx t dh data hold time min. 0 0 ns t oes output enable setup time min. 0 0 ns t oeh output enable hold time read min. 0 0 ns toggle and data polling min. 10 10 ns t ghwl t ghwl read recover time before write min. 0 0 ns t ghel t ghel read recover time before write (oe high to ce low) min. 0 0 ns t elwl t cs ce setup time min. 0 0 ns t wlel t ws we setup time min. 0 0 ns t wheh t ch ce hold time min. 0 0 ns t ehwh t wh we hold time min. 0 0 ns t wlwh t wp write pulse width min. 35 35 ns t eleh t cp ce pulse width min. 35 35 ns t whwl t wph write pulse width high min. 20 30 ns t ehel t cph ce pulse width high min. 20 30 ns t whwh1 t whwh1 programming operation byte typ. 8.6 8.6 s word 12.6 12.6 t whwh2 t whwh2 sector erase operation (note 1) typ. 4.8 4.8 sec t eoe delay time from embedded output enable max. 75 90 ns t vcs v cc setup time min. 50 50 s t vlht voltage transition time (note 2) min. 4 4 s t wpp write pulse width (note 2) min. 100 100 s t oesp oe setup time to we active (note 2) min. 4 4 s t csp ce setup time to we active (note 2) min. 4 4 s t rb recover time from ry/by min. 0 0 ns t flqz byte switching low to output high-z max. 30 30 ns t fhqv byte switching high to output active min. 40 30 ns
29 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n switching waveforms ? key to switching waveforms figure 5.1 ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h h or l: any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance off state we oe ce t df t ce t oe outputs addresses addresses stable high-z output valid high-z t oeh t acc t rc t oh
30 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 5.2 ac waveforms for page read mode operations a 13 to a 19 addresses valid outputs high-z da a 0 to a 2 (a -1 ) aa ab ac db dc t rc t prc t acc t ce t oe t pacc t oh t pacc t oh t oh t df t oeh we oe ce
31 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) figure 6 ac waveforms for alternate we controlled program operations t ch t wp t whwh1 t wc t ah ce oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out
32 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 7 ac waveforms for alternate ce controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at word address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) t cp t ds t whwh1 t wc t ah we oe addresses data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd
33 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 8 ac waveforms for chip/sector erase operations * : 1. sa is the sector address for sector erase. addresses = 555h (word), aaaah (byte) for chip erase. 2. these waveforms are for the 16 mode. (the addresses differ from 8 mode.) v cc ce oe addresses data we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h 30h for sector erase
34 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 9 ac waveforms for data polling during embedded algorithm operations *:dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce oe we data t df t ch t ce dq 7 = valid data dq 7 * data dq 0 to dq 6 = output flag (t eoe ) dq0 to dq6 valid data high-z high-z dq 7 dq 0 to dq 6 * figure 10 ac waveforms for taggle bit i during embedded algorithm operations * : dq 6 = stops toggling. (the device has completed the embedded operation.) ce we oe data dq 6 = toggle dq 6 = stop toggling dq 0 to dq 7 data valid t oe dq 6 = toggle t oeh t oes t dh dq 6 t oeh
35 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 11 timing diagram for word mode configuration ce byte t elfh t fhqv a -1 dq 0 to dq 7 dq 0 to dq 14 dq 15 dq 15 /a -1 dq 0 to dq 14 figure 12 timing diagram for byte mode configuration ce byte dq 15 / a-1 dq 0 to dq 14 t elfl dq 15 dq 0 to dq 14 dq 0 to dq 7 a -1 t flqz
36 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 13 byte timing diagram for write operations ce the falling edge of the last we signal t hold we (t ah ) t set (t as ) input valid byte
37 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 14 ac waveforms for sector protection timing diagram sax = sector address for initial sector say = sector address for next sector note: a -1 is v il on byte mode. t vlht sax say a 0 a 6 a 9 v id 3 v oe v id 3 v t vlht we ce 01h data a 1 a 19 , a 18 , a 17 t vlht a 16 , a 15 , a 14 a 13 , a 12 t wpp t vlht t oesp t csp t oe v cc t vcs
38 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 15 dq 2 vs. dq 6 note: dq 2 is read from the erase-suspended sector. dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe
39 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n flow chart figure 16 embedded program tm algorithm * : the sequence is applied for 16 mode. the addresses differ from 8 mode. no yes start program command sequence* (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address verify byte ? program address/program data programming completed last address ? yes no
40 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 17 embedded erase tm algorithm * : the sequence is applied for 16 mode. the addresses differ from 8 mode. 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling or toggle bit from device erasure completed chip erase command sequence* (address/command): individual sector/multiple sector* erase command sequence (address/command): sector address/30h sector address/30h sector address/30h start data = ffh no yes ?
41 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 18 data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va =address for programming =any of the sector addresses within the sector being erased during sector erase or multiple erases operation. =any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. fail dq 7 = data? no no dq 7 = data? dq 5 = 1? pass yes yes no start read byte (dq 0 to dq 7 ) addr. = va read byte (dq 0 to dq 7 ) addr. = va yes *
42 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 19 toggle bit algorithm * : dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1. fail dq 6 = toggle ? * yes no dq 6 = toggle dq 5 = 1? pass yes no yes start read byte ? (dq 0 to dq 7 ) addr. = h or l no read (dq 0 to dq 7 ) addr. = h or l
43 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 20 sector protection algorithm * : a -1 is v il on byte mode. setup sector addr. activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes no no plscnt = 1 time out 100 m s read from sector increment plscnt no yes protect another sector? start sector protection data = 01h? plscnt = 25? device failed remove v id from a 9 completed remove v id from a 9 write reset command ( a 1 = v ih , a 0 = v il , oe = v id , a 9 = v id a 6 = ce = v il ( a 19, a 18 , a 17 , a 16, write reset command addr. = sa, a 6 = v il )* a 0 = v il , a 1 = v ih a 15 , a 14 , a 13 , a 12 )
44 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 21 temporary sector unprotection algorithm notes: 1. all protected sectors are unprotected. 2. all previously protected sectors are protected once again. temporary unprotect enable perform erase or program operations temporary unprotect disable start temporary sector unprotection completed (note 2) command write (note 1) command write
45 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 figure 22 embedded programming algorithm for fast mode * : the sequence is applied for 16 mode. * : the addresses differ from 8 mode. yes no 555h/aah verify byte? start 555h/20h 2aah/55h xxxxh/a0h program address/program data data polling device last address ? programming completed xxxh/90h xxxh/f0h increment address yes no set fast mode in fast program reset fast mode
46 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n erase and programming performance n pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 4.8 60 sec excludes programming time prior to erasure byte programming time 8.6 300 s excludes system-level overhead word programming time 12.6 360 chip programming time 18 140 sec excludes system-level overhead erase/program cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 6.0 7.5 pf c out output capacitance v out = 0 8.5 12.0 pf c in2 control pin capacitance v in = 0 8.0 11.5 pf
47 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29pl160 t d -80 pftn device number/description mbm29pl160 16 mega-bit (2m 8-bit or 1m 16-bit) cmos page mode flash memory 3.0 v-only read, write, and erase pa c k a g e t y p e pftn = 48-pin thin small outline package (tsop) standard pinout pftr = 48-pin thin small outline package (tsop) reverse pinout pf =44-pin small outline package (sop) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector
48 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 n package dimensions (continued) c 1996 fujitsu limited f48029s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.10(.004) 0.50?.10 (.020?004) 0.15?.05 (.006?002) 11.50ref (.460) 0.50(.0197) typ 0.20?.10 (.008?004) 0.05(0.02)min .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) (stand off) 1 24 25 48 lead no. * * 12.00?.20 (.472?008) (mounting height) dimensions in mm (inches) 48-pin plastic tsop (i) (fpt-48p-m19) *: resin protruction. (each side: 0.15(.006) max)
49 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 (continued) c 1996 fujitsu limited f48030s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.10(.004) 0.50?.10 (.020?004) 0.15?.10 (.006?002) 11.50(.460)ref 0.50(.0197) typ 0.20?.10 (.008?004) 0.05(0.02)min .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) (stand off) 1 24 25 48 lead no. * * 12.00?.20(.472?008) (mounting height) dimensions in mm (inches) *: resin protrusion. (each side: 0.15(.006) max) 48-pin plastic tsop (i) (fpt-48p-m20)
50 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 c 1998 fujitsu limited f44023s-4c-4 index 0.40 +0.10 ?.05 +.004 ?002 .016 m 0.13(.005) 1.27(.050)typ (.006?002) 13.00?.10 16.00?.20 (.512?004) (.630?008) 0.80?.20 (.031?008) 1 22 23 44 lead no. (stand off) 1.120 ?008 +.010 ?.20 +0.25 28.45 14.40?.20 (.567?008) 0.15?.05 0.10(.004) 26.67(1.050)ref 2.35?.15(.093?006) (mounting height) .008 ?006 +.004 ?.15 +0.10 0.20 dimensions in mm (inches) 44-pin plastic sop (fpt-44p-m16)
51 mbm29pl160td -75/-90 /mbm29pl160bd -75/-90 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9907 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inhereut chance inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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